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isp1181b full-speed universal serial bus peripheral controller rev. 02 07 december 2004 product data 1. general description the isp1181b is a universal serial bus (usb) peripheral controller that complies with universal serial bus speci?cation rev. 2.0 , supporting data transfer at full-speed (12 mbit/s). it provides full-speed usb communication capacity to microcontroller or microprocessor-based systems. the isp1181b communicates with the systems microcontroller or microprocessor through a high-speed general-purpose parallel interface. the isp1181b supports fully autonomous, multi-con?gurable direct memory access (dma) operation. the modular approach to implementing a usb peripheral controller allows the designer to select the optimum system microcontroller from the wide variety available. the ability to reuse existing architecture and ?rmware investments shortens development time, eliminates risks and reduces costs. the result is fast and ef?cient development of the most cost-effective usb peripheral solution. the isp1181b is ideally suited for application in many personal computer peripherals such as printers, communication devices, scanners, external mass storage (zip ? drive) devices and digital still cameras. it offers an immediate cost reduction for applications that currently use scsi implementations. 2. features n complies with universal serial bus speci?cation rev. 2.0 and most device class speci?cations n supports data transfer at full-speed (12 mbit/s) n high performance usb peripheral controller with integrated serial interface engine (sie), fifo memory, transceiver and 3.3 v voltage regulator n high speed (11.1 mbyte/s or 90 ns read/write cycle) parallel interface n fully autonomous and multi-con?guration dma operation n up to 14 programmable usb endpoints with 2 ?xed control in/out endpoints n integrated physical 2462 bytes of multi-con?guration fifo memory n endpoints with double buffering to increase throughput and ease real-time data transfer n seamless interface with most microcontrollers/microprocessors n bus-powered capability with low power consumption and low suspend current n 6 mhz crystal oscillator input with integrated pll for low emi n controllable lazyclock (100 khz 50 %) output during suspend n software controlled connection to the usb bus (softconnect?) n good usb connection indicator that blinks with traf?c (goodlink?)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 2 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. n clock output with programmable frequency (up to 48 mhz) n complies with the acpi?, onnow? and usb power management requirements n internal power-on and low-voltage reset circuit, with possibility of a software reset n operation over the extended usb bus voltage range (4.0 v to 5.5 v) with 5 v tolerant i/o pads n operating temperature range - 40 cto + 85 c n full-scan design with high fault coverage n available in tssop48 and hvqfn48 packages. 3. applications n personal digital assistant (pda) n digital camera n communication device, for example: u router u modem n mass storage device, for example: u zip drive n printer n scanner. 4. ordering information table 1: ordering information type number package name description version isp1181bdgg tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 ISP1181BBS hvqfn48 plastic thermal enhanced very thin quad ?at package; no leads; 48 terminals; body 7 7 0.85 mm sot619-2
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x philips semiconductors isp1181b full-speed usb peripheral controller 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 07 december 2004 3 of 70 5. block diagram fig 1. block diagram. 004aaa134 16 5 1.5 k w isp1181b bus interface analog tx/rx 44 3.3 v reset 3 voltage regulator power-on reset memory management unit integrated ram micro controller handler endpoint handler internal supply i/o pin supply dma handler progr. divider 48 mhz 6 mhz xtal2 to led sense input xtal1 hub goodlink to/from usb to/from microcontroller pll oscillator bit clock recovery philips sie 1 v cc softconnect 10, 12 38, 35 to 27, 24 to 19 eot, dack 15 int internal reset 3.3 v 3.3 v 43 to 39 cs, ale, wr, rd, a0 ad0, data1 to data9, data10 to data15 18 bus_conf1 17 bus_conf0 11 dreq 74847 gl clkout 6 v bus 4 d - 5 d + 45 v reg(3.3) v ref 9 suspend 8 wakeup 2 reggnd 2 3 25, 36, 46 gnd 37 v cc(3.3) 26
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 4 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. pinning information 6.1 pinning fig 2. pin con?guration tssop48. isp1181bdgg 004aaa135 v cc reggnd v reg(3.3) d - d + v bus gl wakeup suspend eot dreq dack int bus_conf0 bus_conf1 data15 data14 data13 data12 data11 data10 xtal1 xtal2 gnd clkout reset cs ale wr rd a0 ad0 v cc(3.3) gnd data1 data2 data3 data4 data5 data6 data7 data8 data9 v ref gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 test1 test2 test3
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 5 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.2 pin description fig 3. pin con?guration hvqfn48. data12 data13 v ref data10 gnd bus_conf1 data11 data14 data15 data9 data7 data8 reggnd clkout xtal2 gnd d + xtal1 d - v cc v reg(3.3) reset ale cs ISP1181BBS 004aaa136 data4 data3 data5 data1 v cc(3.3) a0 data6 data2 gnd ad0 rd wr int dack eot wakeup bus_conf0 test2 test3 test1 dreq suspend gl v bus bottom view 2 1 3 4 5 6 9 7 24 18 16 20 22 23 21 19 17 15 14 13 37 42 39 38 40 41 43 44 46 48 45 47 11 8 10 12 36 34 31 32 35 33 30 29 27 25 28 26 table 2: pin description symbol [1] pin type description tssop48 hvqfn48 v cc 1 44 - supply voltage (3.3 v or 5.0 v) reggnd 2 45 - voltage regulator ground supply v reg(3.3) 3 46 - regulated supply voltage (3.3 v 10 %) from internal regulator; used to connect decoupling capacitor and pull-up resistor on d + line; remark: cannot be used to supply external devices. d - 4 47 ai/o usb d - connection (analog) d + 5 48 ai/o usb d + connection (analog) v bus 61iv bus sensing input gl 7 2 o goodlink led indicator output (open-drain, 8 ma); the led is default on, blinks off upon usb traf?c; to connect an led use a series resistor of 470 w (v cc = 5.0 v) or 330 w (v cc = 3.3 v) wakeup 8 3 i wake-up input (edge triggered, low to high); generates a remote wake-up from suspend state suspend 9 4 o suspend state indicator output (4 ma); used as power switch control output (active low) for powered-off application
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 6 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. eot 10 5 i end-of-transfer input (programmable polarity, see ta b l e 2 1 ); used by the dma controller to force the end of a dma transfer to the isp1181b dreq 11 6 o dma request output (4 ma; programmable polarity, see ta b l e 2 1 ); signals to the dma controller that the isp1181b wants to start a dma transfer dack 12 7 i dma acknowledge input (programmable polarity, see ta b l e 2 1 ); used by the dma controller to signal the start of a dma transfer requested by the isp1181b test1 13 8 i test input; this pin must be connected to v cc via an external 10 k w resistor test2 14 9 i test input; this pin must be connected to v cc via an external 10 k w resistor int 15 10 o interrupt output; programmable polarity (active high or low) and signalling (level or pulse); see ta b l e 2 1 test3 16 11 o test output; this pin is used for test purposes only bus_conf0 17 12 i bus con?guration selector; see ta b l e 3 bus_conf1 18 13 i bus con?guration selector; see ta b l e 3 data15 19 14 i/o bit 15 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data14 20 15 i/o bit 14 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data13 21 16 i/o bit 13 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data12 22 17 i/o bit 12 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data11 23 18 i/o bit 11 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data10 24 19 i/o bit 10 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) gnd 25 20 - ground supply v ref 26 21 - i/o pin reference voltage (3.3 v); no connection if v cc = 5.0 v data9 27 22 i/o bit 9 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data8 28 23 i/o bit 8 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data7 29 24 i/o bit 7 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data6 30 25 i/o bit 6 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) table 2: pin description continued symbol [1] pin type description tssop48 hvqfn48
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 7 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. data5 31 26 i/o bit 5 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data4 32 27 i/o bit 4 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data3 33 28 i/o bit 3 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data2 34 29 i/o bit 2 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) data1 35 30 i/o bit 1 of d[15:0]; bidirectional data line (slew-rate controlled output, 4 ma) gnd 36 31 - ground supply v cc(3.3) 37 32 - supply voltage (3.0 v to 3.6 v); leave this pin unconnected when using v cc = 5.0 v ad0 38 33 i/o multiplexed bidirectional address and data line; represents address a0 or bit 0 of d[15:0] in conjunction with input ale; level-sensitive input or slew-rate controlled output (4 ma) address phase : a high-to-low transition on input ale latches the level on this pin as address a0 (1 = command, 0 = data) data phase : during reading this pin outputs bit d[0]; during writing the level on this pin is latched as bit d[0] a0 39 34 i address input; selects command (a0 = 1) or data (a0 = 0); in a multiplexed address/data bus con?guration this pin is not used and must be tied low (connect to gnd) rd 40 35 i read strobe input wr 41 36 i write strobe input ale 42 37 i address latch enable input; a high-to-low transition latches the level on pin ad0 as address information in a multiplexed address/data bus con?guration; must be tied low (connect to gnd) for a separate address/data bus con?guration cs 43 38 i chip select input reset 44 39 i reset input (schmitt trigger); a low level produces an asynchronous reset; connect to v cc for power-on reset (internal por circuit) clkout 45 40 o programmable clock output (2 ma) table 2: pin description continued symbol [1] pin type description tssop48 hvqfn48
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 8 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] symbol names with an overscore (for example, name) represent active low signals. gnd 46 41 - ground supply xtal2 47 42 o crystal oscillator output (6 mhz); connect a fundamental parallel-resonant crystal; leave this pin open when using an external clock source on pin xtal1 xtal1 48 43 i crystal oscillator input (6 mhz); connect a fundamental parallel-resonant crystal or an external clock source (leave pin xtal2 unconnected) table 2: pin description continued symbol [1] pin type description tssop48 hvqfn48
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 9 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. functional description the isp1181b is a full-speed usb peripheral controller with up to 14 con?gurable endpoints. it has a fast general-purpose parallel interface for communication with many types of microcontrollers or microprocessors. it supports different bus con?gurations (see ta b l e 3 ) and local dma transfers of up to 16 bytes per cycle. the block diagram is given in figure 1 . the isp1181b has 2462 bytes of internal fifo memory, which is shared among the enabled usb endpoints. the type and fifo size of each endpoint can be individually con?gured, depending on the required packet size. isochronous and bulk endpoints are double-buffered for increased data throughput. the isp1181b requires a single supply voltage of 3.3 v or 5.0 v and has an internal 3.3 v voltage regulator for powering the analog usb transceiver. it supports bus-powered operation. the isp1181b operates on a 6 mhz oscillator frequency. a programmable clock output is available up to 48 mhz. during suspend state the 100 khz 50 % lazyclock frequency can be output. 7.1 analog transceiver the transceiver is compliant with the universal serial bus speci?cation rev. 2.0 (full speed) . it interfaces directly with the usb cable through external termination resistors. 7.2 philips serial interface engine (sie) the philips sie implements the full usb protocol layer. it is completely hardwired for speed and needs no ?rmware intervention. the functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit (de-)stuf?ng, crc checking/generation, packet identi?er (pid) veri?cation/generation, address recognition, handshake evaluation/generation. 7.3 memory management unit (mmu) and integrated ram the mmu and the integrated ram provide the conversion between the usb speed (12 mbit/s bursts) and the parallel interface to the microcontroller (max. 12 mbyte/s). this allows the microcontroller to read and write usb packets at its own speed. 7.4 softconnect the connection to the usb is accomplished by bringing d + (for full-speed usb peripherals) high through a 1.5 k w pull-up resistor. in the isp1181b, the 1.5 k w pull-up resistor is integrated on-chip and is not connected to v cc by default. the connection is established by a command sent from the external/system microcontroller. this allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the usb. reinitialization of the usb connection can also be performed without disconnecting the cable. the isp1181b will check for usb v bus availability before the connection can be established. v bus sensing is provided through pin v bus .
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 10 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. v bus sensing prevents the peripheral from wake-up when v bus is not present. without v bus sensing, any activity or noise on (d+, d-) might wake up the peripheral. with v bus sensing, (d+, d-) is decoupled when no v bus is present. therefore, even if there is noise on the (d+, d-) lines, it is not taken into account. this ensures that the peripheral remains in the suspend state. remark: note that the tolerance of the internal resistors is 25 %. this is higher than the 5 % tolerance speci?ed by the usb speci?cation. however, the overall voltage speci?cation for the connection can still be met with a good margin. the decision to make use of this feature lies with the usb equipment designer. 7.5 goodlink indication of a good usb connection is provided at pin gl through goodlink technology. during enumeration, the led indicator will blink on momentarily. when the isp1181b has been successfully enumerated (the peripheral address is set), the led indicator will remain permanently on. upon each successful packet transfer (with ack) to and from the isp1181b, the led will blink off for 100 ms. during suspend state, the led will remain off. this feature provides a user-friendly indication of the status of the usb peripheral, the connected hub, and the usb traf?c. it is a useful ?eld diagnostics tool for isolating faulty equipment. it can therefore help to reduce ?eld support and hotline overhead. 7.6 bit clock recovery the bit clock recovery circuit recovers the clock from the incoming usb data stream using a 4 times over-sampling principle. it is able to track jitter and frequency drift as speci?ed by the usb speci?cation rev. 2.0 . 7.7 voltage regulator a 5 v-to-3.3 v voltage regulator is integrated on-chip to supply the analog transceiver and internal logic. this voltage is available at pin v reg(3.3) to supply an external 1.5 k w pull-up resistor on the d + line. alternatively, the isp1181b provides softconnect technology via an integrated 1.5 k w pull-up resistor (see section 7.4 ). 7.8 pll clock multiplier a 6 mhz to 48 mhz clock multiplier phase-locked loop (pll) is integrated on-chip. this allows for the use of a low-cost 6 mhz crystal, which also minimizes emi. no external components are required for the operation of the pll. 7.9 parallel i/o (pio) and direct memory access (dma) interface a generic pio interface is de?ned for speed and ease-of-use. it also allows direct interfacing to most microcontrollers. to a microcontroller, the isp1181b appears as a memory device with an 8/16-bit data bus and a 1-bit address line. the isp1181b supports both multiplexed and non-multiplexed address and data buses. the isp1181b can also be con?gured as a dma slave device to allow more ef?cient data transfer. one of the 14 endpoint fifos may directly transfer data to/from the local shared memory. the dma interface can be con?gured independently from the pio interface.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 11 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. modes of operation the isp1181b has four bus con?guration modes, selected via pins bus_conf1 and bus_conf0: mode 0 16-bit i/o port shared with 16-bit dma port mode 1 reserved mode 2 8-bit i/o port shared with 8-bit dma port mode 3 reserved. the bus con?gurations for each of these modes are given in ta b l e 3 . typical interface circuits for each mode are given in section 22.1 . 9. endpoint descriptions each usb peripheral is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ?ow between the host and the peripheral. at design time each endpoint is assigned a unique number (endpoint identi?er, see ta b l e 4 ). the combination of the peripheral address (given by the host during enumeration), the endpoint number and the transfer direction allows each endpoint to be uniquely referenced. the isp1181b has 16 endpoints: endpoint 0 (control in and out) plus 14 con?gurable endpoints, which can be individually de?ned as interrupt/bulk/isochronous, in or out. each enabled endpoint has an associated fifo, which can be accessed either via the parallel i/o interface or via dma. 9.1 endpoint access ta b l e 4 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support dma access. fifo dma access is selected and enabled via bits epidx[3:0] and dmaen of the dma con?guration register. a detailed description of the dma operation is given in section 10 . table 3: bus con?guration modes mode bus_conf[1:0] pio width dma width description dmawd = 0 dmawd = 1 0 0 0 d[15:1], ad0 - d[15:1], ad0 multiplexed address/data on pin ad0; bus is shared by 16-bit i/o port and 16-bit dma port 1 0 1 reserved reserved reserved reserved 2 1 0 d[7:1], ad0 d[7:1], ad0 - multiplexed address/data on pin ad0; bus is shared by 8-bit i/o port and 8-bit dma port 3 1 1 reserved reserved reserved reserved
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 12 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] the total amount of fifo storage allocated to enabled endpoints must not exceed 2462 bytes. [2] in: input for the usb host (isp1181b transmits); out: output from the usb host (isp1181b receives). the data ?ow direction i s determined by bit epdir in the endpoint con?guration register. 9.2 endpoint fifo size the size of the fifo determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared fifo storage, disabled endpoints have zero bytes. ta b l e 5 lists the programmable fifo sizes. the following bits in the endpoint con?guration register (ecr) affect fifo allocation: ? endpoint enable bit (fifoen) ? size bits of an enabled endpoint (ffosz[3:0]) ? isochronous bit of an enabled endpoint (ffoiso). remark: register changes that affect the allocation of the shared fifo storage among endpoints must not be made while valid data is present in any fifo of the enabled endpoints. such changes will render all fifo contents unde?ned . table 4: endpoint access and programmability endpoint identi?er fifo size (bytes) [1] double buffering i/o mode access dma mode access endpoint type 0 64 (?xed) no yes no control out [2] 0 64 (?xed) no yes no control in [2] 1 programmable supported supported supported programmable 2 programmable supported supported supported programmable 3 programmable supported supported supported programmable 4 programmable supported supported supported programmable 5 programmable supported supported supported programmable 6 programmable supported supported supported programmable 7 programmable supported supported supported programmable 8 programmable supported supported supported programmable 9 programmable supported supported supported programmable 10 programmable supported supported supported programmable 11 programmable supported supported supported programmable 12 programmable supported supported supported programmable 13 programmable supported supported supported programmable 14 programmable supported supported supported programmable
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 13 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. each programmable fifo can be con?gured independently via its ecr, but the total physical size of all enabled endpoints (in plus out) must not exceed 2462 bytes. ta b l e 6 shows an example of a con?guration ?tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the peripheral hardware and is transparent to the user. table 5: programmable fifo size ffosz[3:0] non-isochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 6: memory con?guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64 byte ?xed) 64 64 control out (64 byte ?xed) 2046 1023 double-buffered 1023-byte isochronous endpoint 16 16 16-byte interrupt out 16 16 16-byte interrupt in 128 64 double-buffered 64-byte bulk out 128 64 double-buffered 64-byte bulk in
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 14 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9.3 endpoint initialization in response to the standard usb request, set interface, the ?rmware must program all 16 ecrs of the isp1181b in sequence (see ta b l e 4 ), whether the endpoints are enabled or not. the hardware will then automatically allocate fifo storage space. if all endpoints have been con?gured successfully, the ?rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con?guration, the ?rmware must stall the control in endpoint. when reset by hardware or via the usb bus, the isp1181b disables all endpoints and clears all ecrs, except for the control endpoint which is ?xed and always enabled. endpoint initialization can be done at any time; however, it is valid only after enumeration. 9.4 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the interrupt register (ir) will be set by the sie. the ?rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit will be cleared by reading the endpoint status register (esr). the esr also contains information on the status of the endpoint buffer. for an out (= receive) endpoint, the packet length and packet data can be read from isp1181b using the read buffer command. when the whole packet has been read, the ?rmware sends a clear buffer command to enable the reception of new packets. for an in (= transmit) endpoint, the packet length and data to be sent can be written to isp1181b using the write buffer command. when the whole packet has been written to the buffer, the ?rmware sends a validate buffer command to enable data transmission to the host. 9.5 special actions on control endpoints control endpoints require special ?rmware actions. the arrival of a setup packet ?ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command to both control endpoints. this ensures that the last setup packet stays in the buffer and that no packets can be sent back to the host until the microcontroller has explicitly acknowledged that it has seen the setup packet.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 15 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. dma transfer direct memory access (dma) is a method to transfer data from one location to another in a computer system, without intervention of the central processor (cpu). many different implementations of dma exist. the isp1181b supports two methods: ? 8237 compatible mode : based on the dma subsystem of the ibm personal computers (pc, at and all its successors and clones); this architecture uses the intel 8237 dma controller and has separate address spaces for memory and i/o ? dack-only mode : based on the dma implementation in some embedded risc processors, which has a single address space for both memory and i/o. the isp1181b supports dma transfer for all 14 con?gurable endpoints (see ta b l e 4 ). only one endpoint at a time can be selected for dma transfer. the dma operation of the isp1181b can be interleaved with normal i/o mode access to other endpoints. the following features are supported: ? single-cycle or burst transfers (up to 16 bytes per cycle) ? programmable transfer direction (read or write) ? multiple end-of-transfer (eot) sources: external pin, internal conditions, short/empty packet ? programmable signal levels on pins dreq, dack and eot. 10.1 selecting an endpoint for dma transfer the target endpoint for dma access is selected via bits epdix[3:0] in the dma con?guration register, as shown in ta b l e 7 . the transfer direction (read or write) is automatically set by bit epdir in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). asserting input dack automatically selects the endpoint speci?ed in the dma con?guration register, regardless of the current endpoint used for i/o mode access. table 7: endpoint selection for dma transfer endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write 10 1011 out: read in: write 11 1100 out: read in: write
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 16 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.2 8237 compatible mode the 8237 compatible dma mode is selected by clearing bit dakoly in the hardware con?guration register (see ta b l e 2 0 ). the pin functions for this mode are shown in ta b l e 8 . the dma subsystem of an ibm compatible pc is based on the intel 8237 dma controller. it operates as a ?y-by dma controller: the data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of isp1181b in 8237 compatible dma mode is given in figure 4 . the 8237 has two control signals for each dma channel: dreq (dma request) and d a ck (dma acknowledge). general control signals are hrq (hold request) and hlda (hold acknowledge). the bus operation is controlled via memr (memory read), memw (memory write), ior (i/o read) and io w (i/o write). 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write table 7: endpoint selection for dma transfer continued endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 table 8: 8237 compatible mode: pin functions symbol description i/o function dreq dma request o isp1181b requests a dma transfer dack dma acknowledge i dma controller con?rms the transfer eot end of transfer i dma controller terminates the transfer rd read strobe i instructs isp1181b to put data on the bus wr write strobe i instructs isp1181b to get data from the bus fig 4. isp1181b in 8237 compatible dma mode. ad0, data1 to data15 cpu 004aaa137 ram isp1181b dma controller 8237 dreq dack dreq hrq hlda hrq hlda dack ior iow memr memw rd wr
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 17 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. the following example shows the steps which occur in a typical dma transfer: 1. isp1181b receives a data packet in one of its endpoint fifos; the packet must be transferred to memory address 1234h. 2. isp1181b asserts the dreq signal requesting the 8237 for a dma transfer. 3. the 8237 asks the cpu to release the bus by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 now sets its address lines to 1234h and activates the memw and ior control signals. 6. the 8237 asserts d a ck to inform the isp1181b that it will start a dma transfer. 7. the isp1181b now places the byte or word to be transferred on the data bus lines, because its rd signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then de-asserts memw and ior. this latches and stores the byte or word at the desired memory location. it also informs the isp1181b that the data on the bus lines has been transferred. 9. the isp1181b de-asserts the dreq signal to indicate to the 8237 that dma is no longer needed. in single cycle mode this is done after each byte or word, in burst mode following the last transferred byte or word of the dma cycle. 10. the 8237 de-asserts the d a ck output indicating that the isp1181b must stop placing data on the bus. 11. the 8237 places the bus control signals ( memr, memw, ior and io w) and the address lines in three-state and de-asserts the hrq signal, informing the cpu that it has released the bus. 12. the cpu acknowledges control of the bus by de-asserting hlda. after activating the bus control lines ( memr, memw, ior and io w) and the address lines, the cpu resumes the execution of instructions. for a typical bulk transfer the above process is repeated 64 times, once for each byte. after each byte the address register in the dma controller is incremented and the byte counter is decremented. when using 16-bit dma, the number of transfers is 32 and address incrementing and byte counter decrementing is done by 2 for each word. 10.3 dack-only mode the dack-only dma mode is selected by setting bit dakoly in the hardware con?guration register (see ta b l e 2 0 ). the pin functions for this mode are shown in ta b l e 9 . a typical example of isp1181b in dack-only dma mode is given in figure 5 . table 9: dack-only mode: pin functions symbol description i/o function dreq dma request o isp1181b requests a dma transfer dack dma acknowledge i dma controller con?rms the transfer; also functions as data strobe eot end-of-transfer i dma controller terminates the transfer rd read strobe i not used wr write strobe i not used
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 18 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. in dack-only mode the isp1181b uses the dack signal as data strobe. input signals rd and wr are ignored. this mode is used in cpu systems that have a single address space for memory and i/o access. such systems have no separate memw and memr signals: the rd and wr signals are also used as memory data strobes. 10.4 end-of-transfer conditions 10.4.1 bulk endpoints a dma transfer to/from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the dma con?guration register, see ta b l e 2 4 ): ? an external end-of-transfer signal occurs on input eot ? the dma transfer completes as programmed in the dma counter register (cntren = 1) ? a short packet is received on an enabled out endpoint (shortp = 1) ? dma operation is disabled by clearing bit dmaen. external eot: when reading from an out endpoint, an external eot will stop the dma operation and clear any remaining data in the current fifo. for a double- buffered endpoint the other (inactive) buffer is not affected. when writing to an in endpoint, an eot will stop the dma operation and the data packet in the fifo (even if it is smaller than the maximum packet size) will be sent to the usb host at the next in token. dma counter register: an eot from the dma counter register is enabled by setting bit cntren in the dma con?guration register. the isp1181b has a 16-bit dma counter register, which speci?es the number of bytes to be transferred. when dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dma counter register. when the internal counter completes the transfer as programmed in the dma counter, an eot condition is generated and the dma operation stops. fig 5. isp1181b in dack-only dma mode. ram isp1181b dma controller cpu dreq dack hrq hlda hrq hlda dreq dack rd wr 004aaa138 ad0, data1 to data15
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 19 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. short packet: normally, the transfer byte count must be set via a control endpoint before any dma transfer takes place. when a short packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short packet in the data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short packet at an out token will stop the dma operation after transferring the data bytes of this packet. [1] the dma transfer stops. however, no interrupt is generated. 10.4.2 isochronous endpoints a dma transfer to/from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the dma con?guration register, see ta b l e 2 4 ): ? an external end-of-transfer signal occurs on input eot ? the dma transfer completes as programmed in the dma counter register (cntren = 1) ? an end-of-packet (eop) signal is detected ? dma operation is disabled by clearing bit dmaen. table 10: summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint eot input eot is active eot is active dma counter register transfer completes as programmed in the dma counter register transfer completes as programmed in the dma counter register short packet short packet is received and transferred counter reaches zero in the middle of the buffer dmaen bit in dma con?guration register dmaen = 0 [1] dmaen = 0 [1] table 11: recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint eot input active do not use preferred dma counter register zero do not use preferred end-of-packet preferred do not use
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 20 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. suspend and resume 11.1 suspend conditions the isp1181b detects a usb suspend status when a constant idle state is present on the usb bus for more than 3 ms. the bus-powered devices that are suspended must not consume more than 500 m a of current. this is achieved by shutting down power to system components or supplying them with a reduced voltage. the steps leading up to suspend status are as follows: 1. on detecting a wake-up-to-suspend transition, the isp1181b sets bit suspnd in the interrupt register. this will generate an interrupt if bit iesusp in the interrupt enable register is set. 2. when the ?rmware detects a suspend condition, it must prepare all system components for the suspend state: a. all signals connected to the isp1181b must enter appropriate states to meet the power consumption requirements of the suspend state. b. all input pins of the isp1181b must have a cmos low or high level. 3. in the interrupt service routine, the ?rmware must check the current status of the usb bus. when bit bustatus in the interrupt register is logic 0, the usb bus has left the suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit clkrun in the hardware con?guration register. 5. when the ?rmware has set and cleared bit gosusp in the mode register, the isp1181b enters the suspend state. in powered-off application, the isp1181b asserts output suspend and switches off the internal clocks after 2 ms. figure 6 shows a typical timing diagram.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 21 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. in figure 6 : ? a : indicates the point at which the usb bus enters the idle state. ? b : indicates resume condition, which can be a 20 ms k-state on the usb bus, a high level on pin wakeup, or a low level on pin cs. ? c : indicates remote wake-up. the isp1181b will drive a k-state on the usb bus for 10 ms after pin wakeup goes high or pin cs goes low. ? d : after detecting the suspend interrupt, set and clear bit gosusp in the mode register. 11.1.1 powered-off application figure 7 shows a typical bus-powered modem application using the isp1181b. the suspend output switches off power to the microcontroller and other external circuits during the suspend state. the isp1181b is woken up through the usb bus (global resume) or by the ring detection circuit on the telephone line. fig 6. suspend and resume timing. 004aaa359 int_n > 5 ms suspend interrupt usb bus gosusp wakeup suspend idle state 10 ms k-state > 3 ms 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms resume interrupt a c d b
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 22 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11.2 resume conditions a wake-up from the suspend state is initiated either by the usb host or by the application: ? usb host : drives a k-state on the usb bus (global resume) ? application : remote wake-up through a high level on input wakeup or a low level on input cs (if enabled using bit wkupcs in the hardware con?guration register). wake-up on cs will work only if v bus is present. the steps of a wake-up sequence are as follows: 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, the clock signals are routed to all internal circuits of the isp1181b. 2. the suspend output is deasserted, and bit resume in the interrupt register is set. this will generate an interrupt if bit ieresm in the interrupt enable register is set. 3. maximum 15 ms after starting the wake-up sequence, the isp1181b resumes its normal functionality. 4. in case of a remote wake-up, the isp1181b drives a k-state on the usb bus for 10 ms. 5. following the deassertion of output suspend, the application restores itself and other system components to the normal operating mode. 6. after wake-up, the internal registers of the isp1181b are write-protected to prevent corruption by inadvertent writing during power-up of external components. the ?rmware must send an unlock device command to the isp1181b to restore its full functionality. 11.3 control bits in suspend and resume fig 7. suspend and wakeup signals in a powered-off modem application. wakeup 8031 rst ring detection isp1181b dp dm usb v bus v bus v cc line 004aaa672 suspend table 12: summary of control bits register bit function interrupt suspnd a transition from awake to the suspend state was detected bustatus monitors usb bus status (logic 1 = suspend); used when interrupt is serviced resume a transition from suspend to the resume state was detected
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 23 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. commands and registers the functions and registers of isp1181b are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in ta b l e 1 3 . a complete access consists of two phases: 1. command phase : when address bit a0 = 1, the isp1181b interprets the data on the lower byte of the bus bits d[7:0] as a command code. commands without a data phase are executed immediately. 2. data phase (optional) : when address bit a0 = 0, the isp1181b transfers the data on the bus to or from a register or endpoint fifo. multi-byte registers are accessed least signi?cant byte/word ?rst. the following applies for register or fifo access in 16-bit bus mode: ? the upper byte (bits d15 to d8) in command phase or the unde?ned byte in data phase are ignored. ? the access of registers is word-aligned: byte access is not allowed. ? if the packet length is odd, the upper byte of the last word in an in endpoint buffer is not transmitted to the host. when reading from an out endpoint buffer, the upper byte of the last word must be ignored by the ?rmware. the packet length is stored in the ?rst 2 bytes of the endpoint buffer. interrupt enable iesusp enables output int to signal the suspend state ieresm enables output int to signal the resume state mode softct enables softconnect pull-up resistor to usb bus gosusp a high-to-low transition enables the suspend state hardware con?guration extpul selects internal (softconnect) or external pull-up resistor wkupcs enables wake-up on low level of input cs pwroff selects powered-off mode during the suspend state unlock all sending data aa37h unlocks the internal registers for writing after a resume table 12: summary of control bits continued register bit function table 13: command and register summary name destination code (hex) transaction [1] initialization commands write control out con?guration endpoint con?guration register endpoint 0 out 20 write 1 byte [2] write control in con?guration endpoint con?guration register endpoint 0 in 21 write 1 byte [2] write endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoint 1 to 14 22 to 2f write 1 byte [2][3] read control out con?guration endpoint con?guration register endpoint 0 out 30 read 1 byte [2]
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 24 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. read control in con?guration endpoint con?guration register endpoint 0 in 31 read 1 byte [2] read endpoint n con?guration (n = 1 to 14) endpoint con?guration register endpoint 1 to 14 32 to 3f read 1 byte [2] write/read device address address register b6/b7 write/read 1 byte [2] write/read mode register mode register b8/b9 write/read 1 byte [2] write/read hardware con?guration hardware con?guration register ba/bb write/read 2 bytes write/read interrupt enable register interrupt enable register c2/c3 write/read 4 bytes write/read dma con?guration dma con?guration register f0/f1 write/read 2 bytes write/read dma counter dma counter register f2/f3 write/read 2 bytes reset device resets all registers f6 - data ?ow commands write control out buffer illegal: endpoint is read-only (00) - write control in buffer fifo endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt/bulk: n 64 bytes read control out buffer fifo endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) - read endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes [4] interrupt/bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoint 1 to 14 42 to 4f - read control out status endpoint status register endpoint 0 out 50 read 1 byte [2] read control in status endpoint status register endpoint 0 in 51 read 1 byte [2] read endpoint n status (n = 1 to 14) endpoint status register n endpoint 1 to 14 52 to 5f read 1 byte [2] validate control out buffer illegal: in endpoints only [5] (60) - validate control in buffer fifo endpoint 0 in [5] 61 - [3] validate endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (in endpoints only) [5] 62 to 6f - [3] clear control out buffer fifo endpoint 0 out 70 - [3] clear control in buffer illegal [6] (71) - clear endpoint n buffer (n = 1 to 14) fifo endpoint 1 to 14 (out endpoints only) [6] 72 to 7f [3] unstall control out endpoint endpoint 0 out 80 - unstall control in endpoint endpoint 0 in 81 - table 13: command and register summary continued name destination code (hex) transaction [1]
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 25 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] with n representing the number of bytes, the number of words for 16-bit bus width is: (n + 1) div 2. [2] when accessing an 8-bit register in 16-bit mode, the upper byte is invalid. [3] in 8-bit bus mode this command requires more time to complete than other commands. see ta b l e 5 8 . [4] during isochronous transfer in 16-bit mode, because n 1023, the ?rmware must take care of the upper byte. [5] validating an out endpoint buffer causes unpredictable behavior of isp1181b. [6] clearing an in endpoint buffer causes unpredictable behavior of isp1181b. [7] reads a copy of the status register: executing this command does not clear any status bits or interrupt bits. 12.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con?gure and enable the embedded endpoints. they also serve to set the usb assigned address of isp1181b and to perform a device reset. 12.1.1 write/read endpoint con?guration this command is used to access the endpoint con?guration register (ecr) of the target endpoint. it de?nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), fifo size and buffering scheme. it also enables the endpoint fifo. the register bit allocation is shown in ta b l e 1 4 . a bus reset will disable all endpoints. the allocation of fifo memory only takes place after all 16 endpoints have been con?gured in sequence (from endpoint 0 out to endpoint 14). although the control endpoints have ?xed con?gurations, they must be included in the initialization sequence and be con?gured with their default values (see ta b l e 4 ). automatic fifo allocation starts when endpoint 14 has been con?gured. unstall endpoint n (n = 1 to 14) endpoint 1 to 14 82 to 8f - check control out status [7] endpoint status image register endpoint 0 out d0 read 1 byte [2] check control in status [7] endpoint status image register endpoint 0 in d1 read 1 byte [2] check endpoint n status (n = 1 to 14) [7] endpoint status image register n endpoint 1 to 14 d2 to df read 1 byte [2] acknowledge setup endpoint 0 in and out f4 - [3] general commands read control out error code error code register endpoint 0 out a0 read 1 byte [2] read control in error code error code register endpoint 0 in a1 read 1 byte [2] read endpoint n error code (n = 1 to 14) error code register endpoint 1 to 14 a2 to af read 1 byte [2] unlock device all registers with write access b0 write 2 bytes write/read scratch register scratch register b2/b3 write/read 2 bytes read frame number frame number register b4 read 1 or 2 bytes read chip id chip id register b5 read 2 bytes read interrupt register interrupt register c0 read 4 bytes table 13: command and register summary continued name destination code (hex) transaction [1]
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 26 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: if any change is made to an endpoint con?guration which affects the allocated memory (size, enable/disable), the fifo memory contents of all endpoints becomes invalid. therefore, all valid data must be removed from enabled endpoints before changing the con?guration. code (hex): 20 to 2f write (control out, control in, endpoint 1 to 14) code (hex): 30 to 3f read (control out, control in, endpoint 1 to 14) transaction write/read 1 byte 12.1.2 write/read device address this command is used to set the usb assigned address in the address register and enable the usb device. the address register bit allocation is shown in ta b l e 1 6 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the address register (accessible by the micro) is not altered by the bus reset. in response to the standard usb request set address the ?rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write/read address register transaction write/read 1 byte table 14: endpoint con?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 15: endpoint con?guration register: bit description bit symbol description 7 fifoen a logic 1 indicates an enabled fifo with allocated memory. a logic 0 indicates a disabled fifo (no bytes allocated). 6 epdir this bit de?nes the endpoint direction (0 = out, 1 = in). it also determines the dma transfer direction (0 = read, 1 = write). 5 dblbuf a logic 1 indicates that this endpoint has double buffering. 4 ffoiso a logic 1 indicates an isochronous endpoint. a logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] selects the fifo size according to ta b l e 5 table 16: address register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 27 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.3 write/read mode register this command is used to access the isp1181b mode register, which consists of 1 byte (bit allocation: see ta b l e 1 8 ). in 16-bit bus mode the upper byte is ignored. the mode register controls the dma bus width, resume and suspend modes, interrupt activity and softconnect operation. it can be used to enable debug mode, where all errors and not acknowledge (nak) conditions will generate an interrupt. code (hex): b8/b9 write/read mode register transaction write/read 1 byte [1] unchanged by a bus reset. table 17: address register: bit description bit symbol description 7 deven a logic 1 enables the device. 6 to 0 devadr[6:0] this ?eld speci?es the usb device address. table 18: mode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol dmawd reserved gosusp reserved intena dbgmod reserved softct reset 0 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 19: mode register: bit description bit symbol description 7 dmawd a logic 1 selects 16-bit dma bus width (bus con?guration modes 0 and 2). a logic 0 selects 8-bit dma bus width. bus reset value: unchanged. 6 - reserved 5 gosusp writing a logic 1 followed by a logic 0 will activate suspend mode. 4 - reserved 3 intena a logic 1 enables all interrupts. bus reset value: unchanged. 2 dbgmod a logic 1 enables debug mode. where all naks and errors will generate an interrupt. a logic 0 selects normal operation, where interrupts are generated on every ack (bulk endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct a logic 1 enables softconnect (see section 7.4 ). this bit is ignored if extpul = 1 in the hardware con?guration register (see ta b l e 2 0 ). bus reset value: unchanged.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 28 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.4 write/read hardware con?guration this command is used to access the hardware con?guration register, which consists of 2 bytes. the ?rst (lower) byte contains the device con?guration and control values, the second (upper) byte holds the clock control bits and the clock division factor. the bit allocation is given in ta b l e 2 0 . a bus reset will not change any of the programmed bit values. the hardware con?guration register controls the connection to the usb bus, clock activity and power supply during suspend state, output clock frequency, dma operating mode and pin con?gurations (polarity, signalling mode). code (hex): ba/bb write/read hardware con?guration register transaction write/read 2 bytes table 20: hardware con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul nolazy clkrun clkdiv[3:0] reset 00100011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol eotpol wkupcs pwroff intlvl intpol reset 01000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 21: hardware con?guration register: bit description bit symbol description 15 - reserved 14 extpul a logic 1 indicates that an external 1.5 k w pull-up resistor is used on pin d + and that softconnect is not used. bus reset value: unchanged. 13 nolazy a logic 1 disables output on pin clkout of the lazyclock frequency (100 khz 50 %) during suspend state. a logic 0 causes pin clkout to switch to lazyclock output after approximately 2 ms delay, following the setting of bit gosusp in the mode register. bus reset value: unchanged. 12 clkrun a logic 1 indicates that the internal clocks are always running, even during suspend state. a logic 0 switches off the internal oscillator and pll, when they are not needed. during suspend state this bit must be made logic 0 to meet the suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp in the mode register. bus reset value: unchanged. 11 to 8 clkdiv[3:0] this ?eld speci?es the clock division factor n, which controls the clock frequency on output clkout. the output frequency in mhz is given by . the clock frequency range is 3 mhz to 48 mhz ( n=0to 15). with a reset value of 12 mhz (n = 3). the hardware design guarantees no glitches during frequency change. bus reset value: unchanged. 7 dakoly a logic 1 selects dack-only dma mode. a logic 0 selects 8237 compatible dma mode. bus reset value: unchanged. 48 n 1 + ()
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 29 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.5 write/read interrupt enable register this command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, sof lost, eot, suspend, resume, reset). a bus reset will not change any of the programmed bit values. the command accesses the interrupt enable register, which consists of 4 bytes. the bit allocation is given in ta b l e 2 2 . code (hex): c2/c3 write/read interrupt enable register transaction write/read 4 bytes 6 drqpol selects dreq signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 5 dakpol selects dack signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 4 eotpol selects eot signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. 3 wkupcs a logic 1 enables remote wake-up via a low level on input cs (for wake-up on cs to work, v bus must be present). bus reset value: unchanged. 2 pwroff a logic 1 enables powering-off during suspend state. output suspend is con?gured as a power switch control signal for external devices (high during suspend). this value should always be initialized to logic 1. bus reset value: unchanged. 1 intlvl selects the interrupt signalling mode on output int (0 = level, 1 = pulsed). in pulsed mode an interrupt produces an 166 ns pulse. see section 13 for details. bus reset value: unchanged. 0 intpol selects int signal polarity (0 = active low, 1 = active high). bus reset value: unchanged. table 21: hardware con?guration register: bit description continued bit symbol description table 22: interrupt enable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 30 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.6 write/read dma con?guration this command de?nes the dma con?guration of isp1181b and enables/disables dma transfers. the command accesses the dma con?guration register, which consists of 2 bytes. the bit allocation is given in ta b l e 2 4 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write/read dma con?guration transaction write/read 2 bytes [1] unchanged by a bus reset. bit 7 6 5 4 3 2 1 0 symbol reserved sp_ieeot iepsof iesof ieeot iesusp ieresm ierst reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 23: interrupt enable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 to 10 iep14 to iep1 a logic 1 enables interrupts from the indicated endpoint. 9 iep0in a logic 1 enables interrupts from the control in endpoint. 8 iep0out a logic 1 enables interrupts from the control out endpoint. 7 - reserved 6 sp_ieeot a logic 1 enables interrupt upon detection of a short packet. 5 iepsof a logic 1 enables 1 ms interrupts upon detection of pseudo sof. 4 iesof a logic 1 enables interrupt upon sof detection. 3 ieeot a logic 1 enables interrupt upon eot detection. 2 iesusp a logic 1 enables interrupt upon detection of suspend state. 1 ieresm a logic 1 enables interrupt upon detection of a resume state. 0 ierst a logic 1 enables interrupt upon detection of a bus reset. table 24: dma con?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reset 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dmaen reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 000 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 31 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.7 write/read dma counter this command accesses the dma counter register, which consists of 2 bytes. the bit allocation is given in ta b l e 2 6 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change the programmed bit values. the internal dma counter is automatically reloaded from the dma counter register when dma is re-enabled (dmaen = 1). see section 12.1.6 for more details. code (hex): f2/f3 write/read dma counter register transaction write/read 2 bytes table 25: dma con?guration register: bit description bit symbol description 15 cntren a logic 1 enables the generation of an eot condition, when the dma counter register reaches zero. bus reset value: unchanged. 14 shortp a logic 1 enables short/empty packet mode. when receiving (out endpoint) a short/empty packet an eot condition is generated. when transmitting (in endpoint) this bit should be cleared. bus reset value: unchanged. 13 to 8 - reserved 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see ta b l e 7 . 3 dmaen writing a logic 1 enables dma transfer, a logic 0 forces the end of an ongoing dma transfer. reading this bit indicates whether dma is enabled (0 = dma stopped, 1 = dma enabled). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes). bus reset value: unchanged. table 26: dma counter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacrh[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacrl[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 32 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.1.8 reset device this command resets the isp1181b in the same way as an external hardware reset via input reset. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none 12.2 data ?ow commands data ?ow commands are used to manage the data transmission between the usb endpoints and the system microcontroller. much of the data ?ow is initiated via an interrupt to the microcontroller. the data ?ow commands are used to access the endpoints and determine whether the endpoint fifos contain valid data. remark: the in buffer of an endpoint contains input data for the host, the out buffer receives output data from the host. 12.2.1 write/read endpoint buffer this command is used to access endpoint fifo buffers for reading or writing. first, the buffer pointer is reset to the beginning of the buffer. following the command, a maximum of (n + 2) bytes can be written or read, n representing the size of the endpoint buffer. for 16-bit access the maximum number of words is (m + 1), with m given by (n + 1) div 2. after each read/write action the buffer pointer is automatically incremented by 1 (8-bit bus width) or by 2 (16-bit bus width). in dma access the ?rst 2 bytes or the ?rst word (the packet length) are skipped: transfers start at the third byte or the second word of the endpoint buffer. when reading, the isp1181b can detect the last byte/word via the eop condition. when writing to a bulk/interrupt endpoint, the endpoint buffer must be completely ?lled before sending the data to the host. exception: when a dma transfer is stopped by an external eot condition, the current buffer content (full or not) is sent to the host. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command data will cause unpredictable behavior of isp1181b. code (hex): 01 to 0f write (control in, endpoint 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoint 1 to 14) transaction write/read maximum (n + 2) bytes (isochronous endpoint: n 1023, bulk/interrupt endpoint: n 32) the data in the endpoint fifo must be organized as shown in ta b l e 2 8 . examples of endpoint fifo access are given in ta b l e 2 9 (8-bit bus) and ta b l e 3 0 (16-bit bus). table 27: dma counter register: bit description bit symbol description 15 to 8 dmacrh[7:0] dma counter register (high byte) 7 to 0 dmacrl[7:0] dma counter register (low byte)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 33 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. remark: there is no protection against writing or reading past a buffers boundary, against writing into an out buffer or reading from an in buffer. any of these actions could cause an incorrect operation. data residing in an out buffer are only meaningful after a successful transaction. exception: during dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 12.2.2 read endpoint status this command is used to read the status of an endpoint fifo. the command accesses the endpoint status register, the bit allocation of which is shown in ta b l e 3 1 . reading the endpoint status register will clear the interrupt bit set for the corresponding endpoint in the interrupt register (see ta b l e 4 8 ). all bits of the endpoint status register are read-only. bit epstal is controlled by the stall/unstall commands and by the reception of a setup token (see section 12.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoint 1 to 14) table 28: endpoint fifo organization byte # (8-bit bus) word # (16-bit bus) description 0 0 (lower byte) packet length (lower byte) 1 0 (upper byte) packet length (upper byte) 2 1 (lower byte) data byte 1 3 1 (upper byte) data byte 2 (n + 1) m = (n + 1) div 2 data byte n table 29: example of endpoint fifo access (8-bit bus width) a0 phase bus lines byte # description 1 command d[7:0] - command code (00h to 1fh) 0 data d[7:0] 0 packet length (lower byte) 0 data d[7:0] 1 packet length (upper byte) 0 data d[7:0] 2 data byte 1 0 data d[7:0] 3 data byte 2 0 data d[7:0] 4 data byte 3 0 data d[7:0] 5 data byte 4 table 30: example of endpoint fifo access (16-bit bus width) a0 phase bus lines word # description 1 command d[7:0] - command code (00h to 1fh) d[15:8] - ignored 0 data d[15:0] 0 packet length 0 data d[15:0] 1 data word 1 (data byte 2, data byte 1) 0 data d[15:0] 2 data word 2 (data byte 4, data byte 3)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 34 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. transaction read 1 byte 12.2.3 stall endpoint/unstall endpoint these commands are used to stall or unstall an endpoint. the commands modify the content of the endpoint status register (see ta b l e 3 1 ). a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the packet content. if the endpoint should stay in its stalled state, the microcontroller can restall it with the stall endpoint command. when a stalled endpoint is unstalled (either by the unstall endpoint command or by receiving a setup token), it is also reinitialized. this ?ushes the buffer: if it is an out buffer it waits for a data 0 pid, if it is an in buffer it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoint 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoint 1 to 14) transaction none table 31: endpoint status register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 32: endpoint status register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). set to logic 1 by a stall endpoint command, cleared to logic 0 by an unstall endpoint command. the endpoint is automatically unstalled upon reception of a setup token. 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data pid, 1 = data1 pid). 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1 the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 35 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.2.4 validate endpoint buffer this command signals the presence of valid data for transmission to the usb host, by setting the buffer full ?ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control in endpoint see section 9.5 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoint 1 to 14) transaction none 12.2.5 clear endpoint buffer this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ?ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint this command switches the current fifo for cpu access. remark: for special aspects of the control out endpoint see section 9.5 . code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoint 1 to 14) transaction none 12.2.6 check endpoint status this command is used to check the status of the selected endpoint fifo without clearing any status or interrupt bits. the command accesses the endpoint status image register, which contains a copy of the endpoint status register. the bit allocation of the endpoint status image register is shown in ta b l e 3 3 . code (hex): d0 to df check status (control out, control in, endpoint 1 to 14) transaction write/read 1 byte table 33: endpoint status image register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 00000000 access rrrrrrrr table 34: endpoint status image register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled, 0 = not stalled). 6 epfull1 a logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 a logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates the data pid of the next packet (0 = data0 pid, 1 = data1 pid).
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 36 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.2.7 acknowledge setup this command acknowledges to the host that a setup packet was received. the arrival of a setup packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microcontroller needs to re-enable these commands by sending an acknowledge setup command, see section 9.5 . code (hex): f4 acknowledge setup transaction none 12.3 general commands 12.3.1 read endpoint error code this command returns the status of the last transaction of the selected endpoint, as stored in the error code register. each new transaction overwrites the previous status information. the bit allocation of the error code register is shown in ta b l e 3 5 . code (hex): a0 to af read error code (control out, control in, endpoint 1 to 14) transaction read 1 byte 3 overwrite this bit is set by hardware, a logic 1 indicating that a new setup packet has overwritten the previous setup information, before it was acknowledged or before the endpoint was stalled. this bit is cleared by reading, if writing the setup data has ?nished. firmware must check this bit before sending an acknowledge setup command or stalling the endpoint. upon reading a logic 1 the ?rmware must stop ongoing setup actions and wait for a new setup packet. 2 setupt a logic 1 indicates that the buffer contains a setup packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer, 1 = secondary buffer). 0 - reserved table 34: endpoint status image register: bit description continued bit symbol description table 35: error code register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00000000 access rrrrrrrr table 36: error code register: bit description bit symbol description 7 unread a logic 1 indicates that a new event occurred before the previous status was read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid, 1 = data1 pid).
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 37 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.3.2 unlock device this command unlocks the isp1181b from write-protection mode after a resume. in suspend state all registers and fifos are write-protected to prevent data corruption by external devices during a resume. also, the register access for reading is possible only after the unlock device command is executed. after waking up from suspend state, the ?rmware must unlock the registers and fifos via this command, by writing the unlock code (aa37h) into the lock register (8-bit bus: lower byte ?rst). the bit allocation of the lock register is given in ta b l e 3 8 . code (hex): b0 unlock the device transaction write 2 bytes (unlock code) 5 - reserved 4 to 1 error[3:0] error code. for error description, see ta b l e 3 7 . 0 rtok a logic 1 indicates that data was received or transmitted successfully. table 37: transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data, or acknowledge), or is a setup token to a non-control endpoint 0100 token crc error 0101 data crc error 0110 time-out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over?ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf?ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored table 36: error code register: bit description continued bit symbol description table 38: lock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlockh[7:0] = aah reset 10101010 access wwwwwwww
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 38 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.3.3 write/read scratch register this command accesses the 16-bit scratch register, which can be used by the ?rmware to save and restore information, for example, the device status before powering down in suspend state. the register bit allocation is given in ta b l e 4 0 . code (hex): b2/b3 write/read scratch register transaction write/read 2 bytes 12.3.4 read frame number this command returns the frame number of the last successfully received sof. it is followed by reading one or two bytes from the frame number register, containing the frame number (lower byte ?rst). the frame number register is shown in ta b l e 4 2 . remark: after a bus reset, the value of the frame number register is unde?ned. bit 7 6 5 4 3 2 1 0 symbol unlockl[7:0] = 37h reset 00110111 access wwwwwwww table 39: lock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks the internal registers and fifos for writing, following a resume. table 40: scratch information register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sfirh[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 41: scratch information register: bit description bit symbol description 15 - reserved; must be logic 0 14 to 8 sfirh[6:0] scratch information register (high byte) 7 to 0 sfirl[7:0] scratch information register (low byte)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 39 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. code (hex): b4 read frame number transaction read 1 or 2 bytes [1] reset value unde?ned after a bus reset. 12.3.5 read chip id this command reads the chip identi?cation code and hardware version number. the ?rmware must check this information to determine the supported functions and features. this command accesses the chip id register, which is shown in ta b l e 4 6 . code (hex): b5 read chip id transaction read 2 bytes table 42: frame number register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sofrh[2:0] reset [1] 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofrl[7:0] reset [1] 00000000 access rrrrrrrr table 43: frame number register: bit description bit symbol description 15 to 11 - reserved 10 to 8 sofrh[2:0] sof frame number (upper byte) 7 to 0 sofrl[7:0] sof frame number (lower byte) table 44: example of frame number register access (8-bit bus width) a0 phase bus lines byte # description 1 command d[7:0] - command code (b4h) 0 data d[7:0] 0 frame number (lower byte) 0 data d[7:0] 1 frame number (upper byte) table 45: example of frame number register access (16-bit bus width) a0 phase bus lines word # description 1 command d[7:0] - command code (b4h) d[15:8] - ignored 0 data d[15:0] 0 frame number table 46: chip id register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 81h access rrrrrrrr
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 40 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12.3.6 read interrupt register this command indicates the sources of interrupts as stored in the 4-byte interrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the interrupt register is shown in ta b l e 4 8 . bit bustatus is used to verify the current bus status in the interrupt service routine. interrupts are enabled via the interrupt enable register, see section 12.1.5 . while reading the interrupt register, read all the 4 bytes completely. code (hex): c0 read interrupt register transaction read 4 bytes bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset 42h access rrrrrrrr table 47: chip id register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (81h) 7 to 0 chipidl[7:0] silicon version (42h, with 42h representing the bcd encoded version number) table 48: interrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus sp_eot psof sof eot suspnd resume reset reset 00000000 access rrrrrrrr table 49: interrupt register: bit description bit symbol description 31 to 24 - reserved 23 to 10 ep14 to ep1 a logic 1 indicates the interrupt source(s): endpoint 14 to 1. 9 ep0in a logic 1 indicates the interrupt source: control in endpoint.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 41 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. interrupts figure 8 shows the interrupt logic of the isp1181b. each of the indicated usb events is logged in a status bit of the interrupt register. corresponding bits in the interrupt enable register determine whether or not an event will generate an interrupt. interrupts can be masked globally by means of the intena bit of the mode register (see ta b l e 1 9 ). the active level and signalling mode of the int output is controlled by the intpol and intlvl bits of the hardware con?guration register (see ta b l e 2 1 ). default settings after reset are active low and level mode. when pulse mode is selected, a pulse of 166 ns is generated when the or-ed combination of all interrupt bits changes from logic 0 to logic 1. 8 ep0out a logic 1 indicates the interrupt source: control out endpoint. 7 bustatus it monitors the current usb bus status (0 = awake, 1 = suspend). 6 sp_eot a logic 1 indicates that an eot interrupt has occurred for a short packet. 5 psof a logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after 3 missed sofs suspend state is entered. 4 sof a logic 1 indicates that a sof condition was detected. 3 eot a logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd a logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume a logic 1 indicates that a resume state was detected. 0 reset a logic 1 indicates that a bus reset condition was detected. table 49: interrupt register: bit description continued bit symbol description
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 42 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. bits reset, resume, sp_eot, eot and sof are cleared upon reading the interrupt register. the endpoint bits (ep0out to ep14) are cleared by reading the associated endpoint status register. bit bustatus follows the usb bus status exactly, allowing the ?rmware to get the current bus status when reading the interrupt register. setup and out token interrupts are generated after isp1181b has acknowledged the associated data packet. in bulk transfer mode, the isp1181b will issue interrupts for every ack received for an out token or transmitted for an in token. in isochronous mode, an interrupt is issued upon each packet transaction. the ?rmware must take care of timing synchronization with the host. this can be done via the pseudo start-of-frame (psof) interrupt, enabled via bit iepsof in the interrupt enable register. if a start-of-frame is lost, psof interrupts are generated every 1 ms. this allows the ?rmware to keep data transfer synchronized with the host. after 3 missed sof events the isp1181b will enter suspend state. an alternative way of handling isochronous data transfer is to enable both the sof and the psof interrupts and disable the interrupt for each isochronous endpoint. fig 8. interrupt logic. mgs772 reset suspnd resume sof ep14 ... ep0in . . . . . . . . . . . . ep0out eot ierst interrupt register interrupt enable register iesusp ieresm iesof iep14 ... iep0in iep0out ieeot device mode register intena intlvl hardware configuration register intpol pulse generator int 1 0
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 43 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. power supply the isp1181b is powered from a single supply voltage, ranging from 4.0 v to 5.5 v. an integrated voltage regulator provides a 3.3 v supply voltage for the internal logic and the usb transceiver. this voltage is available at pin v reg(3.3) for connecting an external pull-up resistor on usb connection d + . see figure 9 . the isp1181b can also be operated from a 3.0 v to 3.6 v supply, as shown in figure 10 . in this case, the internal voltage regulator is disabled and pin v reg(3.3) must be connected to v cc . 15. crystal oscillator and lazyclock the isp1181b has a crystal oscillator designed for a 6 mhz parallel-resonant crystal (fundamental). a typical circuit is shown in figure 11 . alternatively, an external clock signal of 6 mhz can be applied to input xtal1, while leaving output xtal2 open. the 6 mhz oscillator frequency is multiplied to 48 mhz by an internal pll. this frequency is used to generate a programmable clock output signal at pin clkout, ranging from 3 mhz to 48 mhz. in suspend state the normal clkout signal is not available, because the crystal oscillator and the pll are switched off to save power. instead, the clkout signal can be switched to the lazyclock frequency of 100 khz 50 %. the oscillator operation and the clkout frequency are controlled via the hardware con?guration register, as shown in figure 12 . the following bits are involved: ? clkrun switches the oscillator on and off ? clkdiv[3:0] is the division factor determining the normal clkout frequency ? nolazy controls the lazyclock signal output during suspend state. fig 9. isp1181b with a 4.0 v to 5.5 v supply. fig 10. isp1181b with a 3.0 v to 3.6 v supply. v cc v cc(3.3) v reg(3.3) isp1181b 004aaa140 4.0 v to 5.5 v v ref 3.0 v to 3.6 v 004aaa141 v cc v cc(3.3) v reg(3.3) isp1181b v ref fig 11. typical oscillator circuit. clkout 6 mhz 18 pf 18 pf xtal2 xtal1 004aaa142 isp1181b
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 44 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. when isp1181b enters suspend state (by setting and clearing bit gosusp in the mode register), outputs suspend and clkout change state after approximately 2 ms delay. when nolazy = 0, the clock signal on output clkout does not stop, but changes to the 100 khz 50 % lazyclock frequency. when resuming from suspend state by a positive pulse on input wakeup, output suspend is cleared and the clock signal on clkout is restarted after a 0.5 ms delay. the timing of the clkout signal at suspend and resume is given in figure 13 . fig 12. oscillator and lazyclock logic. mgs775 clkrun hardware configuration register clkdiv [ 3:0 ] nolazy ? (n + 1) 1 0 n pll 8 xtal osc lazyclock enable enable 4 nolazy clkout enable 6 mhz 48 mhz suspend . . . . . . 100 (50 %) khz if enabled, the 100 khz 50 % lazyclock frequency will be output on pin clkout during suspend state. fig 13. clkout signal timing at suspend and resume. mgs776 wakeup gosusp 1.8 to 2.2 ms 0.5 ms pll circuit stable 3 to 4 ms suspend clkout
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 45 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 16. power-on reset the isp1181b has an internal power-on reset (por) circuit. input pin reset can be directly connected to v cc . the clock signal on output clkout starts 0.5 ms after power-on and normally requires 3 to 4 ms to stabilize. the triggering voltage of the por circuit is 2.0 v nominal. a por is automatically generated when v cc goes below the trigger voltage for a duration longer than 50 m s. a hardware reset disables all usb endpoints and clears all ecrs, except for the control endpoint which is ?xed and always enabled. section 9.3 explains how to (re-)initialize the endpoints. t 1 : clock is running t 2 : bus_conf pins are sampled t 3 : registers are accessible (1) supply voltage (5 v or 3.3 v), connected externally to pin reset. fig 14. power-on reset timing. mgt026 t 1 t 2 t 3 v cc (1) 2.0 v 0 v 350 m s > 50 m s 1 ms 1 ms por
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 46 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 17. limiting values [1] equivalent to discharging a 100 pf capacitor via a 1.5 k w resistor (human body model). 18. recommended operating conditions table 50: absolute maximum ratings in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 + 6.0 v v i input voltage - 0.5 v cc + 0.5 v i latchup latch-up current v i < 0 or v i >v cc - 100 ma v esd electrostatic discharge voltage i li <1 m a [1] - 2000 v t stg storage temperature - 60 + 150 c p tot total power dissipation v cc = 5.5 v - 165 mw table 51: recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage with regulator 4.0 5.0 5.5 v without regulator 3.0 3.3 3.6 v v i input voltage 0 - v cc v v i(ai/o) input voltage on analog i/o pins (d + /d - ) 0 - 3.6 v v o(od) open-drain output pull-up voltage 0 - v cc v t amb ambient temperature - 40 - + 85 c
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 47 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 19. static characteristics [1] for 3.3 v operation, pin v reg(3.3) must be connected to pin v cc(3.3) . [2] in suspend mode the minimum voltage is 2.7 v. [3] external loading is not included. [1] not applicable for open-drain outputs. table 52: static characteristics; supply pins v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v reg(3.3) regulated supply voltage v cc = 4.0 v to 5.5 v [1] 3.0 [2] 3.3 3.6 v i cc operating supply current v cc = 5.0 v; t amb =25 c - 26 - ma v cc = 3.3 v; t amb =25 c - 22 - ma i cc(susp) suspend supply current v cc = 5.0 v; t amb =25 c--20 [3] m a v cc = 3.3 v; t amb =25 c--70 [3] m a table 53: static characteristics: digital pins v cc = 3.3 v 10 % or 5.0 v 10 %; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = rated drive - - 0.4 v i ol =20 m a - - 0.1 v v oh high-level output voltage i oh = rated drive [1] 2.4 - - v leakage current i li input leakage current - - 5 m a open-drain outputs i oz off-state output current - - 5 m a
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 48 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] d + is the usb positive data pin; d - is the usb negative data pin. [2] includes external resistors of 22 w 1 % on both d + and d - . [3] this voltage is available at pin v reg(3.3) . [4] in suspend mode the minimum voltage is 2.7 v. table 54: static characteristics: analog i/o pins (d + , d - ) [1] v cc = 3.3 v 10 % or 5.0 v 10 %; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d + ) - v i(d - ) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to + 3.6 v - - 0.3 v v oh high-level output voltage r l =15k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current - - 10 m a capacitance c in transceiver capacitance pin to gnd - - 20 pf resistance r pu pull-up resistance on d + softconnect = on 1 - 2 k w z drv [2] driver output impedance steady-state drive 29 - 44 w z inp input impedance 10 - - m w termination v term [3] termination voltage for upstream port pull-up (r pu ) 3.0 [4] - 3.6 v
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 49 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 20. dynamic characteristics [1] dependent on the crystal oscillator start-up time. [1] test circuit: see figure 33 . [2] excluding the ?rst transition from idle state. [3] characterized only, not tested. limits guaranteed by design. table 55: dynamic characteristics v cc = 3.3 v 10 % or 5.0 v 10 %; v gnd =0v; t amb = - 40 cto + 85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w( reset) pulse width on input reset crystal oscillator running 50 - - m s crystal oscillator stopped - 3 [1] -ms crystal oscillator f xtal crystal frequency - 6 - mhz table 56: dynamic characteristics: analog i/o pins (d + , d - ) [1] v cc = 3.3 v 10 % or 5.0 v 10 %; v gnd =0v;t amb = - 40 cto + 85 c; c l = 50 pf; r pu = 1.5 k w on d + to v term ; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l =50pf; 10%to90% of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf; 90%to10% of | v oh - v ol | 4 - 20 ns frfm differential rise/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2][3] 1.3 - 2.0 v data source timing t feopt source eop width see figure 15 [3] 160 - 175 ns t fdeop source differential data-to-eop transition skew see figure 15 [3] - 2- + 5ns receiver timing t jr1 receiver data jitter tolerance for consecutive transitions see figure 16 [3] - 18.5 - + 18.5 ns t jr2 receiver data jitter tolerance for paired transitions see figure 16 [3] - 9- + 9ns t feopr receiver se0 width accepted as eop; see figure 15 [3] 82--ns t fst width of se0 during differential transition rejected as eop; see figure 17 [3] --14ns
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 50 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. t period is the bit duration corresponding with the usb data rate. full-speed timing symbols have a subscript pre?x f, low-speed timings a pre?x l. fig 15. source differential data-to-eop transition skew and eop width. mgr776 t period differential data lines crossover point differential data to se0/eop skew n t period + t deop source eop width: t eopt receiver eop width: t eopr crossover point extended + 3.3 v 0 v t period is the bit duration corresponding with the usb data rate. fig 16. receiver differential data jitter. mgr871 t period t jr differential data lines + 3.3 v 0 v t jr1 t jr2 consecutive transitions n t period + t jr1 paired transitions n t period + t jr2 fig 17. receiver se0 width tolerance. mgr872 differential data lines + 3.3 v 0 v t fst v ih(min)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 51 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21. timing 21.1 parallel i/o timing [1] commands acknowledge setup, clear buffer, validate buffer and write endpoint con?guration require 180 ns to complete. table 57: dynamic characteristics: parallel interface timing symbol parameter conditions 8-bit bus 16-bit bus unit min max min max read timing (see figure 18 ) t rhax address hold time after rd high 0 - 0 - ns t avrl address setup time before rd low 0- 0- ns t shdz data outputs high-impedance time after cs high -3-3ns t rhsh chip deselect time after rd high 0 - 0 - ns t rlrh rd pulse width 25 - 25 - ns t rldv data valid time after rd low - 22 - 22 ns t shrl cs high until next isp1181b rd 60 - 120 - ns t shrl +t rlrh read cycle time 90 - 180 - ns write timing (see figure 19 ) t whax address hold time after wr high 1 - 1 - ns t avwl address setup time before wr low 0- 0- ns t shwl cs high until next isp1181b wr 60 - 120 - ns t shwl +t wlwh write cycle time 90/180 [1] - 180 - ns t wlwh wr pulse width 22 - 22 - ns t whsh chip deselect time after wr high 0 - 0 - ns t dvwh data setup time before wr high 5 - 5 - ns t whdz data hold time after wr high 3 - 3 - ns ale timing (see figure 20 ) t lh ale pulse width 20 - 20 - ns t avll address setup time before ale low 10 - 10 - ns t llax address hold time after ale low reading 0 10 0 10 ns writing 0 - 0 - ns
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 52 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) for t shrl , both cs and rd must be deasserted. fig 18. parallel interface read timing (i/o and 8237 compatible dma). mgs787 a0 t rhax t avrl t rlrh t rldv t shdz t shrl (1) data rd cs/dack t rhsh (1) for t shwl , both cs and wr must be deasserted. fig 19. parallel interface write timing (i/o and 8237 compatible dma). mgs789 cs/dack a0 data wr t whax t avwl t whdz t dvwh t wlwh t whsh t shwl (1)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 53 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21.2 access cycle timing [1] commands acknowledge setup, clear buffer, validate buffer and write endpoint con?guration require 180 ns to complete. fig 20. ale timing. mgs790 ad0 ale data t lh t avll t llax a0 d0 table 58: dynamic characteristics: access cycle timing symbol parameter conditions 8-bit bus 16-bit bus unit min max min max write command + write data (see figure 21 and figure 22 ) t cy(wc-wd) cycle time for write command, then write data 100 [1] - 205 - ns t cy(wd-wd) cycle time for write data 90 - 205 - ns t cy(wd-wc) cycle time for write data, then write command 90 - 205 - ns write command + read data (see figure 23 and figure 24 ) t cy(wc-rd) cycle time for write command, then read data 100 [1] - 205 - ns t cy(rd-rd) cycle time for read data 90 - 205 - ns t cy(rd-wc) cycle time for read data, then write command 90 - 205 - ns fig 21. write command + write data cycle timing. mgt022 t cy(wc-wd) t cy(wd-wd) command data wr data data cs
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 54 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21.3 dma timing: single-cycle mode (1) example: read data. fig 22. write data + write command cycle timing. mgt025 t cy(wd-wc) data data wr data command rd cs (1) fig 23. write command + read data cycle timing. mgt023 t cy(wc-rd) t cy(rd-rd) command data wr data data rd cs (1) example: read data. fig 24. read data + write command cycle timing. mgt024 t cy(rd-wc) data data wr data (1) command rd cs table 59: dynamic characteristics: single-cycle dma timing symbol parameter conditions 8-bit bus 16-bit bus unit min max min max 8237 compatible mode (see figure 25 ) t asrp dreq off after dack on - 40 - 40 ns t cy(dreq) cycle time signal dreq 90 - 180 - ns
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 55 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. read in dack-only mode (see figure 26 ) t asrp dreq off after dack on - 40 - 40 ns t asap dack pulse width 25 - 25 - ns t asap + t aprs dreq on after dack off 90 - 180 - ns t asdv data valid after dack on - 22 - 22 ns t apdz data hold after dack off - 3 - 3 ns write in dack-only mode (see figure 27 ) t asrp dreq off after dack on - 40 - 40 ns t asap + t aprs dreq on after dack off 90 - 180 - ns t dvap data setup before dack off 5 - 5 - ns t apdz data hold after dack off 3 - 3 - ns single-cycle eot (see figure 28 ) t rsih input rd/ wr high after dreq on 22 - 22 - ns t ihap dack off after input rd/ wr high 0- 0- ns t eot eot pulse width eot on; dack on; rd/ wr low 22 - 22 - ns t rlis input eot on after rd low - 22 - 89 ns t wlis input eot on after wr low - 22 - 89 ns table 59: dynamic characteristics: single-cycle dma timing continued symbol parameter conditions 8-bit bus 16-bit bus unit min max min max fig 25. dma timing in 8237 compatible mode. mgs792 dreq dack t asrp t cy(dreq)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 56 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 26. dma read timing in dack-only mode. mgs793 dack dreq t asrp t aprs t asdv t apdz data fig 27. dma write timing in dack-only mode. mgs794 dack dreq t asrp t aprs t dvap t apdz data t asap (1) t asrp starts from d a ck or rd/ wr going low, whichever occurs later. (2) the rd/ wr signals are not used in dack-only dma mode. (3) the eot condition is considered valid if d a ck, rd/ wr and eo t are all active (= low). fig 28. eot timing in single-cycle dma mode. mgs795 dreq t rsih t ihap t asrp (1) t eot (3) t rlis t wlis eot dack rd/wr (2)
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 57 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 21.4 dma timing: burst mode table 60: dynamic characteristics: burst mode dma timing symbol parameter conditions 8-bit bus 16-bit bus unit min max min max burst (see figure 29 ) t rsih input rd/ wr high after dreq on 22 - 22 - ns t ilrp dreq off after input rd/ wr low - 60 - 60 ns t ihap dack off after input rd/ wr high 0- 0- ns t ihil dma burst repeat interval (input rd/ wr high to low) 90 - 180 - ns burst eot (see figure 30 ) t eot eot pulse width eot on; dack on; rd/ wr low 22 - 22 - ns t isrp dreq off after input eot on - 40 - 40 ns t rlis input eot on after rd low - 22 - 89 ns t wlis input eot on after wr low - 22 - 89 ns fig 29. burst mode dma timing. mgs796 dack dreq t rsih t ilrp t ihil t ihap rd/wr
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 58 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) the eot condition is considered valid if d a ck, rd/ wr and eo t are all active (= low). fig 30. eot timing in burst mode dma. mgs797 dack dreq t isrp t eot (1) rd/wr eot t rlis t wlis
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 59 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22. application information 22.1 typical interface circuits (1) 470 w assuming that v cc is 5.0 v. fig 31. typical interface circuit for bus con?guration mode 0 (shared ports: 16-bit pio, 16-bit dma). 004aaa143 22 w 22 w 470 w (1) 0.1 m f 0.1 m f isp1181b h8s/2357 v reg(3.3) a1 v cc v cc 18 pf 6 mhz 18 pf reset v bus d - d+ xtal1 xtal2 gl d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 usb upstream connector data11 data12 data13 data14 data15 ad0 link led a0 ale bus_conf1 bus_conf0 csn cs rd rd wr wr irq int suspend p1.1 wakeup dreq0 dreq dack dack tend eot 4 3 2 1
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 60 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. (1) 470 w assuming that v cc is 5.0 v. fig 32. typical interface circuit for bus con?guration mode 2 (shared ports: 8-bit pio, 8-bit dma). 004aaa144 22 w 22 w 470 w (1) isp1181b 18 pf 6 mhz 18 pf d - d+ xtal1 xtal2 usb upstream connector ad0 link led a0 ale bus_conf1 bus_conf0 int suspend wakeup dreq dack eot dma controller cs1 mcu_rd mcu_wr bus_gnt bus_req cs2 rd wr dreq dack eot d7 d6 d5 d4 d3 d2 d1 d0 4 3 2 1 v reg(3.3) v cc reset v bus gl cs rd wr 0.1 m f 0.1 m f v cc d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d7 d6 d5 d4 d3 d2 d1 d0 8051 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ale psen rd wr irq p2.3 p2.0 p2.1 cs rd wr 8-bit dma port
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 61 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22.2 interfacing isp1181b with an h8s/2357 microcontroller this section gives a summary of the isp1181b interface with a h8s/2357 (or compatible) microcontroller. aspects discussed are: interrupt handling, address mapping, dma and i/o port usage for suspend and remote wake-up control. a typical interface circuit is shown in figure 31 . 22.2.1 interrupt handling ? isp1181b: program the hardware con?guration register to select an active low level for output int (intpol = 0, see ta b l e 2 0 ) ? h8s/2357 : program the irq sense control register (iscrh and iscrl) to specify low-level sensing for the irq input. 22.2.2 address mapping in h8s/2357 the h8s/2357 bus controller partitions its 16 mbyte address space into eight areas (0 to 7) of 2 mbyte each. the bus controller will activate one of the outputs cs0 to cs7 when external address space for the associated area is accessed. the isp1181b can be mapped to any address area, allowing easy interfacing when the isp1181b is the only peripheral in that area. if in the example circuit for bus con?guration mode 0 (see figure 31 ) the isp1181b is mapped to address ffff08h (in area 7), output cs7 of the h8s/2357 can be directly connected to input cs of the isp1181b. the external bus speci?cations, bus width, number of access states and number of program wait states can be programmed for each address area. the recommended settings of h8s/2357 for interfacing the isp1181b are: ? 8-bit bus in bus width control register (abwcr) ? enable wait states in access state control register (astcr) ? 1 program wait state in the wait control register (wcrh and wcrl). 22.2.3 using dma the isp1181b can be con?gured for several methods of dma with the h8s/2357 and other devices. the interface circuit in figure 31 shows an example of the isp1181b working with the h8s/2357 in single-address dack-only dma mode. external devices are not shown. for single-address dack-only mode, ?rmware must program the following settings: ? isp1181b : C program the dma counter register with the total transfer byte count C program the hardware con?guration register to select active level low for dreq and dack C select the target endpoint and transfer direction C select dack-only mode and enable dma transfer.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 62 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 22.2.4 using h8s/2357 i/o ports in the interface circuit of figure 31 pin p1.1 of the h8s/2357 is con?gured as a general purpose output port. this pin drives the isp1181bs wakeup input to generate a remote wake-up. the h8s/2357 has 3 registers to con?gure port 1: port 1 data direction register (p1ddr), port 1 data register (p1dr) and port 1 register (port1). only registers p1ddr and p1dr must be con?gured, register port1 is only used to read the actual levels on the port pins. ? h8s/2357: C select pin p1.1 to be an output in register p1ddr C program the desired bit value for p1.1 in register p1dr. 23. test information the dynamic characteristics of the analog i/o ports (d + and d -) as listed in ta b l e 5 6 , were determined using the circuit shown in figure 33 . load capacitance: c l = 50 pf (full-speed mode) speed: full-speed mode only: internal 1.5 k w pull-up resistor on d + fig 33. load impedance for d + and d - pins. test point c l 50 pf 22 w 15 k w d.u.t mgs784
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 63 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 24. package outline fig 34. tssop48 package outline. unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m q a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a max. 1.2 0 2.5 5 mm scale mo-153
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 64 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 35. hvqfn48 package outline. terminal 1 index area terminal 1 index area 0.5 1 a 4 e h b unit d y e 0.2 c references outline version european projection issue date iec jedec jeita mm 7.15 6.85 d h 5.25 4.95 y 1 7.15 6.85 5.25 4.95 e 1 5.5 e 2 5.5 0.30 0.18 0.80 0.65 a 1 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot619-2 mo-220 - - - - - - e 6.85 6.65 e 1 6.85 6.65 d 1 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot619-2 hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm a max. a a 4 a 1 detail x y y 1 c l e h d h e 13 48 37 36 25 12 1 x d d 1 e e 1 c b a e 2 02-05-17 02-10-22 e e 1 b 24 1/2 e 1/2 e a c c b v m w m c
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 65 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 25. soldering 25.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 25.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 25.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 66 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 25.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 25.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 61: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 67 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
philips semiconductors isp1181b full-speed usb peripheral controller product data rev. 02 07 december 2004 68 of 70 9397 750 13958 ? koninklijke philips electronics n.v. 2004. all rights reserved. 26. revision history table 62: revision history rev date cpcn description 02 20041207 200412003 product data; second version (9397 750 13958). modi?cations: ? updated terminology from device to peripheral, where applicable ? updated to the current document style ? figure 3 pin con?guration hvqfn48. : made cs active low ? section 9.2 endpoint fifo size : removed (512 bytes for non-isochronous fifos) from the second last paragraph ? section 10.2 8237 compatible mode : removed eop from the paragraph before the ?gure ? section 11 suspend and resume : updated the complete section ? table 20 hardware con?guration register: bit allocation and table 21 hardware con?guration register: bit description : changed bit name from ckdiv to clkdiv ? added table 43 frame number register: bit description ? created a separate section for recommended operating conditions ? section 21 timing : removed the ?rst section on timing symbols ? table 57 dynamic characteristics: parallel interface timing : updated values for parameters t rhax and t whax . added parameters t shrl and t shwl . 01 20020703 - product data; initial version (9397 750 09566).
9397 750 13958 philips semiconductors isp1181b full-speed usb peripheral controller ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 02 07 december 2004 69 of 70 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 27. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 28. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 29. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 30. trademarks acpi is an open industry speci?cation for pc power management, co-developed by intel corp., microsoft corp. and toshiba goodlink is a trademark of koninklijke philips electronics n.v. onnow is a trademark of microsoft corp. softconnect is a trademark of koninklijke philips electronics n.v. zip is a registered trademark of iomega corp. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the netherlands all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 07 december 2004 document order number: 9397 750 13958 contents philips semiconductors isp1181b full-speed usb peripheral controller 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 analog transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 philips serial interface engine (sie) . . . . . . . . . . . . . 9 7.3 memory management unit (mmu) and integrated ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.4 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.5 goodlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.6 bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.7 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.8 pll clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.9 parallel i/o (pio) and direct memory access (dma) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 endpoint descriptions. . . . . . . . . . . . . . . . . . . . . . . . 11 9.1 endpoint access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.2 endpoint fifo size . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.3 endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . 14 9.4 endpoint i/o mode access . . . . . . . . . . . . . . . . . . . . 14 9.5 special actions on control endpoints . . . . . . . . . . . . 14 10 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10.1 selecting an endpoint for dma transfer . . . . . . . . . . 15 10.2 8237 compatible mode. . . . . . . . . . . . . . . . . . . . . . . 16 10.3 dack-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.4 end-of-transfer conditions. . . . . . . . . . . . . . . . . . . . 18 10.4.1 bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.4.2 isochronous endpoints . . . . . . . . . . . . . . . . . . . . . . . 19 11 suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1 suspend conditions . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.1.1 powered-off application . . . . . . . . . . . . . . . . . . . . . . 21 11.2 resume conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.3 control bits in suspend and resume. . . . . . . . . . . . . 22 12 commands and registers . . . . . . . . . . . . . . . . . . . . . 23 12.1 initialization commands . . . . . . . . . . . . . . . . . . . . . . 25 12.1.1 write/read endpoint con?guration . . . . . . . . . . . . . 25 12.1.2 write/read device address . . . . . . . . . . . . . . . . . . . 26 12.1.3 write/read mode register. . . . . . . . . . . . . . . . . . . . 27 12.1.4 write/read hardware con?guration . . . . . . . . . . . . 28 12.1.5 write/read interrupt enable register . . . . . . . . . . . 29 12.1.6 write/read dma con?guration . . . . . . . . . . . . . . . . 30 12.1.7 write/read dma counter . . . . . . . . . . . . . . . . . . . . 31 12.1.8 reset device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.2 data ?ow commands . . . . . . . . . . . . . . . . . . . . . . . . 32 12.2.1 write/read endpoint buffer . . . . . . . . . . . . . . . . . . . 32 12.2.2 read endpoint status . . . . . . . . . . . . . . . . . . . . . . . 33 12.2.3 stall endpoint/unstall endpoint . . . . . . . . . . . . . . . . 34 12.2.4 validate endpoint buffer . . . . . . . . . . . . . . . . . . . . . . 35 12.2.5 clear endpoint buffer . . . . . . . . . . . . . . . . . . . . . . . . 35 12.2.6 check endpoint status . . . . . . . . . . . . . . . . . . . . . . . 35 12.2.7 acknowledge setup . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.3 general commands . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.3.1 read endpoint error code . . . . . . . . . . . . . . . . . . . . 36 12.3.2 unlock device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12.3.3 write/read scratch register . . . . . . . . . . . . . . . . . . 38 12.3.4 read frame number . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.5 read chip id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3.6 read interrupt register . . . . . . . . . . . . . . . . . . . . . . 40 13 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 14 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15 crystal oscillator and lazyclock . . . . . . . . . . . . . . . 43 16 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 17 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 18 recommended operating conditions . . . . . . . . . . . . 46 19 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 47 20 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 49 21 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.1 parallel i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.2 access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.3 dma timing: single-cycle mode . . . . . . . . . . . . . . . . 54 21.4 dma timing: burst mode . . . . . . . . . . . . . . . . . . . . . . 57 22 application information . . . . . . . . . . . . . . . . . . . . . . . 59 22.1 typical interface circuits . . . . . . . . . . . . . . . . . . . . . . 59 22.2 interfacing isp1181b with an h8s/2357 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.1 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.2 address mapping in h8s/2357 . . . . . . . . . . . . . . . . . 61 22.2.3 using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22.2.4 using h8s/2357 i/o ports . . . . . . . . . . . . . . . . . . . . 62 23 test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 25 soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 25.1 introduction to soldering surface mount packages . . 65 25.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 25.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 25.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 25.5 package related soldering information . . . . . . . . . . . 66 26 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 27 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 28 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 29 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 30 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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